1. Field of the Invention
The present invention relates generally electronic circuit design, and more specifically to controlling an output data rate of an electronic circuit.
2. Description of the Related Art
An application specific integrated circuit (ASIC) is a chip, or portion thereof, that is custom designed for a specific application, as opposed to a general-purpose chip such as a microprocessor. Since the ASIC is designed for a specific application, the ASIC can be optimally configured to provide improved performance of the specific application as compared to the general-purpose chip. In other words, since the general-purpose chip requires overhead that is not necessary for the specific application, the general-purpose chip is less optimized (i.e., slower) for the specific application as compared to the ASIC. Fully customized ASIC chips use a custom-designed mask for each layer in the chip, thus design and fabrication of ASIC chips can be quite time consuming and costly. Therefore, it is beneficial in the ASIC design process to develop a prototype of the ASIC for testing prior to fabrication of the actual ASIC.
One method for developing the prototype of the ASIC involves the use of a field programmable gate array (FPGA). The FPGA is a type of gate array that can be programmed outside of a semiconductor fabrication operation (i.e., in the field). The FPGA is an integrated circuit containing a number of logic cells that can each be independently programmed to perform one of a number of functions. The number of logic cells are interconnected by a network of wires and programmable switches. The number of logic cells and associated interconnects can be programmed to define basic circuitry building blocks that can then be combined to create a complex circuit. Thus, the FPGA can be programmed to represent a prototype of an ASIC.
Once the FPGA prototype of the ASIC is developed, testing is performed using the FPGA prototype to evaluate the functionality and performance of the ASIC design. Thus, the FPGA prototype testing can be used to identify and correct problems that may be present in the ASIC design prior to investment of substantial time and money in fabricating the ASIC. In order to ensure applicability of FPGA prototype test results to the ultimate ASIC design, it is desirable to have the same logic in the FPGA prototype as that intended to be put in the ASIC. Also, in order to simulate the actual operating conditions of the ASIC using the FPGA prototype, it is desirable to have the same data output rate from both the FPGA prototype and the ASIC. However, due to fundamental differences between the FPGA and the ASIC, conventional methods for using the FPGA prototype to test the ASIC design have not been able to simultaneously maintain the same logic and the same data output rate between both the ASIC and the FPGA prototype.
More specifically, since the programmable gate arrays of the FPGA prototype operate slower that the “hard-wired” ASIC circuitry, the FPGA prototype is required to operate at a slower clock speed relative to the ASIC. Consequently, the data output rate of the FPGA prototype is slower than the data output rate of the ASIC. Since the clock speed of the FPGA prototype cannot be increased sufficiently to match the ASIC data output rate, conventional methods have included modifying the FPGA prototype logic to achieve a data output rate that more closely matches the ASIC data output rate. However, as previously mentioned, introducing differences between the logic of the FPGA prototype and the logic of the ASIC increases a probability that the FPGA prototype performance will not be truly representative of the ASIC design. Also, each time a different ASIC data output rate is to be simulated by the FPGA prototype, the FPGA prototype logic has to be re-modified.
In view of the foregoing, a method and an apparatus is needed for maintaining equivalent logic between an ASIC and a corresponding FPGA prototype while achieving an equivalent data output rate from each of the ASIC and the FPGA prototype.